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#include "ops_asmgen.h"Go to the source code of this file.
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| #define | LOOP_VH(s, mask, idx) if (s->use_vh) LOOP(mask, idx) |
| #define | LOOP_MASK_VH(s, p, idx) if (s->use_vh) LOOP_MASK(p, idx) |
| #define | LOOP_MASK_BWD_VH(s, p, idx) if (s->use_vh) LOOP_MASK_BWD(p, idx) |
| #define | CMT(comment) rasm_annotate(r, comment) |
| #define | CMTF(fmt, ...) rasm_annotatef(r, (char[128]){0}, 128, fmt, __VA_ARGS__) |
| #define | MAX_SAVED_REGS 12 |
| #define | PRINT_SWIZZLE_V(n, vh) print_swizzle_v((char[8]){ 0 }, n, vh) |
Definition at line 27 of file ops_asmgen.c.
Definition at line 28 of file ops_asmgen.c.
| #define LOOP_MASK_BWD_VH | ( | s, | |
| p, | |||
| idx | |||
| ) | if (s->use_vh) LOOP_MASK_BWD(p, idx) |
Definition at line 29 of file ops_asmgen.c.
| #define CMT | ( | comment | ) | rasm_annotate(r, comment) |
Definition at line 32 of file ops_asmgen.c.
| #define CMTF | ( | fmt, | |
| ... | |||
| ) | rasm_annotatef(r, (char[128]){0}, 128, fmt, __VA_ARGS__) |
Definition at line 33 of file ops_asmgen.c.
| #define MAX_SAVED_REGS 12 |
Definition at line 112 of file ops_asmgen.c.
| #define PRINT_SWIZZLE_V | ( | n, | |
| vh | |||
| ) | print_swizzle_v((char[8]){ 0 }, n, vh) |
Definition at line 432 of file ops_asmgen.c.
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Definition at line 36 of file ops_asmgen.c.
Referenced by asmgen_op_cps(), and asmgen_op_expand().
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Definition at line 47 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 54 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 63 of file ops_asmgen.c.
Referenced by asmgen_epilogue(), and asmgen_prologue().
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Definition at line 68 of file ops_asmgen.c.
Referenced by asmgen_process().
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Definition at line 89 of file ops_asmgen.c.
Referenced by asmgen_process().
Definition at line 114 of file ops_asmgen.c.
Referenced by clobbered_gprs().
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Definition at line 122 of file ops_asmgen.c.
Referenced by asmgen_process().
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The process function for aarch64 works similarly to the x86 backend. The description in x86/ops_include.asm mostly holds as well here.
Definition at line 139 of file ops_asmgen.c.
Referenced by asmgen_process_cps().
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Definition at line 215 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 244 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 266 of file ops_asmgen.c.
Referenced by asmgen_op_read_packed().
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Definition at line 277 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 286 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 310 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 334 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 357 of file ops_asmgen.c.
Referenced by asmgen_op_write_packed().
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Definition at line 368 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 377 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 398 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 424 of file ops_asmgen.c.
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Definition at line 434 of file ops_asmgen.c.
Referenced by swizzle_emit().
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Definition at line 443 of file ops_asmgen.c.
Referenced by asmgen_op_move().
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Definition at line 456 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 467 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 509 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 557 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 575 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 593 of file ops_asmgen.c.
Referenced by asmgen_op_clear().
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Definition at line 612 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Since each instruction in the convert operation needs specific element types, it is simpler to use arrangement specifiers for each operand instead of reshaping all vectors.
This function assumes block_size is either 8 or 16, and that we're always using the most amount of vector registers possible. Therefore, u32 always uses the high vector bank.
Definition at line 630 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 728 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 771 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 794 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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Definition at line 817 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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The intermediate registers for fmul+fadd (for when SWS_BITEXACT is set) start from temp vector 8.
The non-zero coefficients have been packed in aarch64_setup_linear() in sequential order into the individual lanes of the coefficient vector registers. We must follow the same order of execution here.
Most modern aarch64 cores have a fastpath for sequences of fmla instructions. This means that even if the coefficient is 1, it is still faster to use fmla by 1 instead of fadd.
Split the multiply-accumulate into fmul+fadd. All multiplications are performed first into temporary registers, and only then added to the destination, to reduce the dependency chain. There is no need to perform multiplications by 1.
Definition at line 841 of file ops_asmgen.c.
Referenced by asmgen_op_linear().
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Definition at line 910 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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For a description of the matrix buffer layout, read the comments in aarch64_setup_dither() in aarch64/ops.c.
Sort components by y_offset value so that we can start dithering with the smallest value, and increment the pointer upwards for each new offset. The dither matrix is over-allocated and may be over-read at the top, but it cannot be over-read before the start of the buffer. Since we only mask the y offset once, this would be an issue if we tried to subtract a value larger than the initial y_offset.
We use ubfiz to mask and shift left in one single instruction: ubfiz <Wd>, <Wn>, #<lsb>, #<width> Wd = (Wn & ((1 << width) - 1)) << lsb;
Given: block_size = 8, log2(block_size) = 3 dither_size = 16, log2(dither_size) = 4, dither_mask = 0b1111 sizeof(float) = 4, log2(sizeof(float)) = 2
Suppose we have bx = 0bvvvv. To get x, we left shift by log2(block_size) and end up with 0bvvvv000. Then we mask against dither_mask, and end up with 0bv000. Finally we multiply by sizeof(float), which is the same as shifting left by log2(sizeof(float)). The result is 0bv00000.
Therefore: width = log2(dither_size) - log2(block_size) lsb = log2(block_size) + log2(sizeof(float))
The ubfiz instruction for the y offset performs masking by the dither matrix size and shifts by the stride.
On subsequent runs, just increment the pointer. The matrix is over-allocated, so we don't risk overreading.
Definition at line 922 of file ops_asmgen.c.
Referenced by asmgen_op_cps().
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